SSA-based Register Allocation for GPU Architectures (xdc2021)

SSA-based register allocation is a new strategy for register allocation which decouples register allocation from spilling and guarantees predictable register usage. It holds special promise for GPUs due to common architectural features like dynamic register sharing, but there are also challenges in real-world implementations. After first being used in Mesa by the ACO compiler backend for AMD GPUs, it is now also in use by the Freedreno driver for Qualcomm Adreno GPUs. In this talk we will explain the basic concepts, considerations for real-world implementations, and implementation choices made in freedreno and ACO. about this event: https://c3voc.de